A method for forming a transistor of a semiconductor device

专利摘要:
PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of improving integration degree by using an isolation region of matrix type. CONSTITUTION: A trench as an isolation region is formed at a silicon substrate(31) so as to define an active region. At this time, the side of the trench is adjacent to the side of the active region, thereby forming a matrix-type trench. A protrudent SEG(Selective Epitaxial Growth) layer(45) is formed by using the silicon substrate of the trench as a seed. An insulating spacer(47,49) is formed at both sidewalls of the SEG layer(45). At this time, the protrudent active region of the SEG and the active region of the substrate are isolated by the insulating spacer(47,49).
公开号:KR20030088573A
申请号:KR1020020026232
申请日:2002-05-13
公开日:2003-11-20
发明作者:김종수
申请人:주식회사 하이닉스반도체；
IPC主号:

专利说明:

A method for forming a transistor of a semiconductor device
[13] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to minimize the area of a device isolation layer defining an active region, thereby enabling high integration of the device and using the same in unit cells and switching devices.
[14] A typical device isolation layer is provided with an isolation layer between active regions provided on one side or the other side of a word line along a word line.
[15] In general, the device isolation layer is formed in a trench type.
[16] 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the prior art, and generally illustrates a case in which an active region is formed in an I or Z shape and a trench type isolation film is formed therebetween.
[17] Referring to FIG. 1, an isolation layer 13 defining an active region is formed on a silicon substrate 11.
[18] In this case, the device isolation layer 13 forms a pad oxide film and a nitride film on the silicon substrate 11 and a photolithography process using a device isolation mask (not shown) to form the nitride film, the pad oxide film, and the silicon substrate 11 having a predetermined thickness. ) To form a trench and then bury it.
[19] Next, the gate electrode 17 is formed on the active region of the silicon substrate 11.
[20] In this case, a gate oxide film 15 is interposed between the gate electrode 17 and the silicon substrate 11.
[21] Subsequently, a low concentration of impurity junction regions (not shown) are formed by ion implanting low concentrations of impurities into the silicon substrate 11 using the gate electrode 17 as a mask.
[22] An insulating film spacer 19 is formed on the sidewalls of the gate electrode 17 and a high concentration of impurities are implanted into the silicon substrate 11 using the gate electrode 17 and the insulating film spacer 19 as masks. A source / drain junction region (not shown) is formed by forming an impurity junction region (not shown).
[23] Then, an interlayer insulating film (not shown) is formed over the entire surface, and source / drain electrodes 21 and 23 connected to the junction region are formed through the interlayer insulating film.
[24] As described above, the manufacturing method of the semiconductor device according to the related art does not satisfy the high integration of the device, and in order to solve the problem, a step is formed in the device isolation region and an insulating film spacer is formed on the boundary of the step, but the contact margin is secured. There is a problem that can not be.
[25] In order to solve the problems of the related art, the device isolation layer region defining the active region is formed in a trench shape, an insulating layer spacer is formed on the sidewalls of the trench, and an epitaxial layer selectively formed on the trench is formed to form another active region. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a device is formed in a matrix form in which active regions are separated by insulating film spacers.
[1] 1 is a cross-sectional view showing a semiconductor device according to the prior art.
[2] 2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
[3] 3 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.
[4] <Explanation of Signs of Major Parts of Drawings>
[5] 11,31 silicon substrate 13: device isolation film
[6] 15,51 gate oxide film 17,53 gate electrode
[7] 19 insulating film spacer 21 source electrode
[8] 23 drain electrode 33 pad oxide film
[9] 35 first nitride film 37 photosensitive film pattern
[10] 39: trench 41,47: thermal oxide film
[11] 43,49: second nitride film 45: selective epitaxial growth layer
[12] 55 source / drain electrodes
[26] In order to achieve the above object, a semiconductor device manufacturing method according to the present invention,
[27] Forming a pad oxide film and a nitride film stacked structure on the silicon substrate;
[28] A trench, which is an isolation region defining an active region having a rectangular structure, is formed on the silicon substrate in a rectangular structure, and the sides of the active region and the sides of the trench are adjacent to each other and formed in a matrix form not adjacent to the same region. Process to do,
[29] Forming an insulation spacer on the sidewalls of the trench;
[30] Forming a selective epitaxial growth layer using the silicon substrate of the trench bottom as a seed, and protruding the upper portion of the nitride film;
[31] Planarizing etching the selective epitaxial growth layer using the laminated structure as an etch barrier layer;
[32] Removing the laminated structure;
[33] Forming an insulating film spacer on sidewalls of the selective epitaxial growth layer to isolate the active region formed of the selective epitaxial growth layer from the active region formed of the semiconductor substrate with the insulating film spacer;
[34] Forming a gate oxide film on the surface of the selective epitaxial growth layer and the semiconductor substrate;
[35] A gate electrode is formed on the silicon substrate and a source / drain is formed by an impurity implantation process using the same. A source is formed on one side of the gate electrode and a drain is formed on the other side, and the drain is a source of a neighboring gate electrode. The process used,
[36] Forming a transistor including forming a lower insulating layer over the entire surface and forming a source / drain electrode connected to the source / drain through the lower insulating layer;
[37] The insulating film spacer is formed of a laminated structure of an oxide film and a nitride film,
[38] The planar etching process is performed by a CMP process,
[39] The transistor is used as a display conversion device using one transistor as a separate unit system.
[40] On the other hand, the principle of the present invention is as follows.
[41] Forming a trench by etching an I-shaped device isolation region defining an active region as an I-type in a rectangular form, and forming a selective epitaxial growth layer filling the trench using a silicon substrate of the trench bottom as a seed, By forming an insulating film spacer between the device isolation region and the active region before and after the formation of the selective epitaxial growth layer, the active region formed of the selective epitaxial growth layer and the active region formed of the silicon substrate are adjacent to each other in the device isolation region. It is to minimize the size of the device by forming a matrix-type active region that does not neighbor each other,
[42] Each transistor can be used as an individual unit system like any display converter.
[43] Here, one side of the word line passing through each active region is used as a source and the other side is used as a drain, and the other side is used as a source of neighboring word lines.
[44] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
[45] 2A through 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and are shown along the cutting line ⓐ-ⓐ of FIG. 2B.
[46] Referring to FIG. 2A, a lamination structure of a pad oxide film 33 and a first nitride film 35 is formed on a silicon substrate 31.
[47] The photoresist pattern 37 is formed on the stack structure.
[48] In this case, the photoresist pattern 37 is an exposure designed in a rectangular matrix so that the first region and the second region that are not etched together use sides, and the first region and the second region are not adjacent to each other. It formed by exposing and developing using a mask.
[49] Referring to FIG. 2B, the trench 39 is formed by etching the stacked structure and the silicon substrate 31 having a predetermined thickness using the photoresist pattern as a mask.
[50] Then, the remaining photoresist pattern 37 is removed during the etching process.
[51] Referring to FIG. 2C, a thermal oxide layer 41 is formed on the surface of the trench 39.
[52] Then, the second nitride film 43 is deposited to a predetermined thickness on the entire surface including the trench 39.
[53] Referring to FIG. 2D, the second nitride layer 43 and the thermal oxide layer 41 are entirely etched perpendicularly to the silicon substrate 31 to etch the thermal oxide layer 41 and the second nitride layer 43 at the bottom of the trench 39. ) To expose the silicon substrate 31 at the bottom of the trench 39, and form an insulating layer spacer formed on the sidewalls of the trench 39 in a lamination structure of the thermal oxide film 41 and the second nitride film 43. do.
[54] Referring to FIG. 2E, an epitaxial growth layer 45 is formed by epitaxially growing the exposed silicon substrate 31 as a seed.
[55] In this case, the selective epitaxial growth layer 45 is grown to fill the trench 39 and protrude upward from the first nitride layer 35.
[56] Next, the selective epitaxial growth layer 45 is planarized by using the stacked structure as an etch barrier layer.
[57] In this case, the planarization etching process is performed by a CMP process.
[58] Next, the laminated structures 33 and 35 are removed.
[59] Then, a thermal oxide film 47 is formed on the surface of the silicon substrate 31 and the selective epitaxial growth layer 45 in which the stacked structures 33 and 35 are removed.
[60] Referring to FIG. 2F, a third nitride film 49 is deposited on the entire surface, and anisotropic etching of the third nitride film 49 and the thermal oxide film 47 is performed on the sidewalls of the selective epitaxial growth layer 45. An insulating film spacer formed of the stacked structure of the 47 and the third nitride film 49 is formed.
[61] Referring to FIGS. 2G, 2H and 2I, the gate oxide layer 51 is formed by thermally oxidizing the surface of the silicon substrate 31 and the selective epitaxial growth layer 45.
[62] A gate electrode 53 is formed on the gate oxide film 51.
[63] In this case, the gate electrode 53 forms the gate oxide layer 51 and the conductive layer for the gate electrode, and forms the gate electrode conductive layer and the gate oxide layer 51 by a photolithography process using a gate electrode mask (not shown). It is formed by etching.
[64] Then, impurities are implanted into the silicon substrate 31 using the gate electrode 53 as a mask to form a source / drain junction region (not shown). The impurity implanted region is used as a source or a drain of a neighboring word line.
[65] At this time, between neighboring source / drain junction regions are formed as insulating spacers having a stacked structure of thermal oxide films 41 and 47 and second and third nitride films 43 and 49 and separated from each other.
[66] A lower insulating layer (not shown) is then formed to form a source / drain electrode that is connected to the source / drain.
[67] Here, "55" shows the source / drain electrodes and is used as the source electrode or the drain electrode depending on the position of the gate electrode 53.
[68] 3A and 3B are plan views showing FIGS. 2A to 2G, wherein FIGS. 2A to 2G show a manufacturing process along a cutting plane of ⓐ-ⓐ in FIG. 3B, and FIGS. 2H and 2I are respectively shown. It is shown along the ⓑ-ⓑ, ⓒ-ⓒ cutting surface of Figure 3b.
[69] As described above, the method of manufacturing a semiconductor device according to the present invention,
[70] A matrix having an active region formed of a rectangular epitaxial growth layer and a semiconductor substrate adjacent to each other and adjacent to the sides of the same active region, each having an insulating region spacer and having an active region isolated from each other. Forming the device in the form enables the high integration of the device and provides an effect that can be applied to the memory device and the switching device.

权利要求:
Claims (4)
[1" claim-type="Currently amended] Forming a pad oxide film and a nitride film stacked structure on the silicon substrate;
A trench, which is an isolation region defining an active region having a rectangular structure, is formed on the silicon substrate in a rectangular structure, and the sides of the active region and the sides of the trench are adjacent to each other and formed in a matrix form not adjacent to the same region. Process to do,
Forming an insulation spacer on the sidewalls of the trench;
Forming a selective epitaxial growth layer using the silicon substrate of the trench bottom as a seed, and protruding the upper portion of the nitride film;
Planarizing etching the selective epitaxial growth layer using the laminated structure as an etch barrier layer;
Removing the laminated structure;
Forming an insulating film spacer on sidewalls of the selective epitaxial growth layer to isolate the active region formed of the selective epitaxial growth layer from the active region formed of the semiconductor substrate with the insulating film spacer;
Forming a gate oxide film on the surface of the selective epitaxial growth layer and the semiconductor substrate;
A gate electrode is formed on the silicon substrate and a source / drain is formed by an impurity implantation process using the same. A source is formed on one side of the gate electrode and a drain is formed on the other side, and the drain is a source of a neighboring gate electrode. The process used,
And forming a lower insulating layer over the entire surface and forming a source / drain electrode connected to the source / drain through the lower insulating layer.
[2" claim-type="Currently amended] The method of claim 1,
The insulating film spacer is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of an oxide film and a nitride film.
[3" claim-type="Currently amended] The method of claim 1,
The planarization etching process is a manufacturing method of a semiconductor device, characterized in that the CMP process.
[4" claim-type="Currently amended] The method of claim 1,
And the transistor is used as a display conversion device using one transistor as a separate unit system.

类似技术:

---

公开号 | 公开日 | 专利标题

---

US8633529B2|2014-01-21|Vertical transistors

---

US8237221B2|2012-08-07|Semiconductor device and method of manufacturing semiconductor device

---

KR100578130B1|2006-05-10|Multi silicon fins for finfet and method for fabricating the same

---

TWI254453B|2006-05-01|Trench DMOS device with improved drain contact

---

US7652331B2|2010-01-26|Semiconductor device and method for fabricating the same

---

JP5391423B2|2014-01-15|Sub-resolution silicon features and methods for forming the same

---

US6835981B2|2004-12-28|Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions

---

TWI400757B|2013-07-01|Methods for forming shielded gate field effect transistors

---

TWI396284B|2013-05-11|Field effect transistor and method for manufacturing the same

---

US6406962B1|2002-06-18|Vertical trench-formed dual-gate FET device structure and method for creation

---

US8106464B2|2012-01-31|Semiconductor device having bar type active pattern

---

US5306935A|1994-04-26|Method of forming a nonvolatile stacked memory

---

KR100456691B1|2004-11-10|Semiconductor device having dual isolation structure and method of fabricating the same

---

KR100577565B1|2006-05-08|and method for manufacturing fin Field Effect Transistor

---

KR100862816B1|2008-10-13|Semiconductor device and method of manufacturing the same

---

KR100379612B1|2003-04-08|Shallow trench isolation type semiconductor device and method of forming the same

---

JP3860672B2|2006-12-20|Transistor manufacturing method and transistor manufactured by the manufacturing method

---

CN101952958B|2013-11-13|Systems and devices including fin transistors and methods of using, making, and operating the same

---

US6949801B2|2005-09-27|Dual trench isolation using single critical lithographic patterning

---

TWI692871B|2020-05-01|Semiconductor structure and method of forming the same

---

KR100675285B1|2007-01-29|Semiconductor device having vertical transistor and method of fabricating the same

---

KR100437011B1|2004-06-23|Method of forming semiconductor device having metal silicide layer

---

KR100506055B1|2005-08-05|Method for manufacturing transistor of semiconductor device

---

KR100541047B1|2006-01-11|Double-gate MOS transistor and method of fabricating the same

---

KR20040029582A|2004-04-08|MOS Transistor having multiple channels and method of manufacturing the same

同族专利:

---

公开号 | 公开日

---

JP2003332414A|2003-11-21|

---

JP4161195B2|2008-10-08|

---

KR100426442B1|2004-04-13|

---

TW200306648A|2003-11-16|

---

US6737688B2|2004-05-18|

---

US20030211683A1|2003-11-13|

---

TWI230441B|2005-04-01|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

法律状态:
2002-05-13|Application filed by 주식회사 하이닉스반도체

---

2002-05-13|Priority to KR20020026232A

---

2003-11-20|Publication of KR20030088573A

---

2004-04-13|Application granted

---

2004-04-13|Publication of KR100426442B1

优先权:

---

申请号 | 申请日 | 专利标题

---

KR20020026232A|KR100426442B1|2002-05-13|2002-05-13|A method for forming a transistor of a semiconductor device|